In a prior microprocessor integrated circuit chip, it is necessary to distribute a clock signal across the entire microprocessor chip for timing reference. Typically, a prior microprocessor includes a plurality of functional units integrated on the chip. These functional units typically include a register unit, an execution unit, an instruction cache, a data cache and/or a memory management unit.
Typically, the clock signal is generated from a signal clock input. This is typically accomplished by coupling a clock input signal of the microprocessor chip to a global driver circuit. The global driver circuit then couples the clock signal to various units of the microprocessor via a plurality of clock distribution lines.
One disadvantage associated with this prior clock signal distribution network in the microprocessor chip is that the clock signal distribution network introduces different delays to the clock signal (i.e., clock skew). The clock skew occurs when the clock signal distribution network has different clock delays. The factors that cause the clock skew are the electromagnetic propagation delays, buffer delays in the distribution network, and the RC delays in the clock distribution lines of the distribution network. The clock skew also varies from chip to chip due to process variations, temperature variations, power supply variations, and different loading capacitances.
Another disadvantage associated with such prior clock signal distribution network is that the inherent RC delay varies significantly from one clock distribution line to another when the die size of the microprocessor chip increases. As is known, the advances in semiconductor processing technology have made it possible to integrated more functional units into the prior microprocessor integrated circuit chip. The technology advances have also increased the clock frequencies of the prior microprocessor to provide higher speed, higher performance microprocessor. The increase in the die size of the microprocessor chip has caused some of the clock distribution lines to be very long to reach their respective units while some of the clock distribution lines are very short to reach their respective units. This results in the RC delays in the clock lines to be in a wider range that is more difficult to deal with. The higher frequency of the clock signal introduced to the microprocessor also makes the RC delays more significant.
A further disadvantage associated with the clock signal distribution network employed in the microprocessor is the load capacitance in each of the units of the microprocessor. The load capacitance also contributes to the clock skew in the clock signal distribution network. The load capacitance varies from unit to unit because different functional units integrated on the chip introduce different load capacitances.